M0564LE4AE Datasheet, PDF (73/161 Pages) List of Unclassifed Manufacturers – 32-BIT MICROCONTROLLER

0x3FFF_FFFF
M0564
Reserved
0x2000_5000
0x2000_4FFF
20K byte
SRAM bank0
0x2000_0000
20K byte device
Figure 6.2-9 SRAM Memory Organization
6.2.7 Register Lock
Some of the system control registers need to be protected to avoid inadvertent write and disturb the
chip operation. These system control registers are protected after the power-on reset till user to
disable register protection. For user to program these protected registers, a register protection disable
sequence needs to be followed by a special programming. The register protection disable sequence is
writing the data “59h”, “16h” “88h” to the register SYS_REGLCTL address at 0x5000_0100
continuously. Any different data value, different sequence or any other write to other address during
these three data writing will abort the whole sequence.
After the protection is disabled, user can check the protection disable bit at address 0x5000_0100 bit0,
1 is protection disable, and 0 is protection enable. Then user can update the target protected register
value and then write any data to the address “0x5000_0100” to enable register protection.
6.2.8 Auto Trim
This chip supports auto-trim function: the HIRC trim (48 MHz and 22.1184 MHz RC oscillator),
May 05, 2017
Page 73 of 161
Rev 1.00