M0564LE4AE Datasheet, PDF (16/161 Pages) List of Unclassifed Manufacturers – 32-BIT MICROCONTROLLER

M0564
SPI Mode
I²S Mode
SPI_CLK
I2S_BCLK
SPI_SS
SPI_MOSI
I2S_LRCLK
I2S_DO
SPI_MISO
I2S_DI
-
I2S_MCLK
–
–
 I²C
SPI Mode
 Supports Master or Slave mode operation
 Configurable bit length of a transfer word from 8 to 32-bit
 Provides separate 4-/8-level depth transmit and receive FIFO buffers
 Supports MSB first or LSB first transfer sequence
 Supports Byte Reorder function
 Supports PDMA transfer
I²S Mode
 Supports Master or Slave mode operation
 Capable of handling 8-, 16-, 24- and 32-bit word sizes in I2S mode
 Provides separate 4-level depth transmit and receive FIFO buffers in I2S mode
 Supports monaural and stereo audio data in I2S mode
 Supports PCM mode A, PCM mode B, I2S and MSB justified data format in I2S
mode
 Supports PDMA transfer
– Supports up to two sets of I2C device
– Supports Master/Slave mode
– Supports bidirectional data transfer between masters and slaves
– Supports multi-master bus (no central master)
– Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
– Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
– Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
– Supports 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up
and timer-out counter overflows
– Programmable clocks allow versatile rate control
– Supports multiple address recognition, four slave address with mask option
– Supports two-level buffer function
– Supports setup/hold time programmable
– Supports wake-up function
 ADC
– Supports 12-bit SAR ADC
– 12-bit resolution and 10-bit accuracy is guaranteed
– Analog input voltage range: 0~ AV_DD
– Supports external VREF pin
– Up to 20 single-end analog input channels
– Maximum ADC peripheral clock frequency is 16 MHz
– Conversion rate up to 800K SPS at 5V
– Configurable ADC internal sampling time
– Supports single-scan, single-cycle-scan, and continuous scan and scan on enabled
channels
– Supports individual conversion result register with valid and overrun indicators for each
May 05, 2017
Page 16 of 161
Rev 1.00