M0564LE4AE Datasheet, PDF (154/161 Pages) List of Unclassifed Manufacturers – 32-BIT MICROCONTROLLER

M0564
8.6 I2C Dynamic Characteristics
Symbol
Parameter
Standard Mode^[1][2]
Min.
Max.
Fast Mode^[1][2]
Min.
Max.
Unit
tLOW
SCL low period
4.7
-
1.2
-
uS
tHIGH SCL high period
4
-
0.6
-
uS
tSU; STA Repeated START condition setup time
4.7
-
1.2
-
uS
tHD; STA START condition hold time
4
-
0.6
-
uS
tSU; STO STOP condition setup time
tBUF
Bus free time
4
-
4.7^[3]
-
0.6
1.2^[3]
-
uS
-
uS
tSU;DAT
tHD;DAT
Data setup time
Data hold time
250
-
0^[4]
3.45^[5]
100
-
nS
0^[4]
0.8^[5]
uS
tr
SCL/SDA rise time
-
1000
20+0.1Cb
300
nS
tf
SCL/SDA fall time
-
300
-
300
nS
Cb
Capacitive load for each bus line
-
400
-
400
pF
Notes:
1. Guaranteed by design, not tested in production.
2. HCLK must be higher than 2 MHz to achieve the maximum standard mode I²C frequency. It must
be higher than 8 MHz to achieve the maximum fast mode I²C frequency.
3. I²C controller must be retriggered immediately at slave mode after receiving STOP condition.
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to
bridge the undefined region of the falling edge of SCL.
5. The maximum hold time of the Start condition has only to be met if the interface does not stretch
the low period of SCL signal.
SDA
SCL
STOP
START
tBUF
tLOW
tr
tf
tHD;STA
tHIGH
tHD;DAT
tSU;DAT
Figure 8.6-1 I²C Timing Diagram
Repeated
START
tSU;STA
STOP
tSU;STO
May 05, 2017
Page 154 of 161
Rev 1.00