M0564LE4AE Datasheet, PDF (101/161 Pages) List of Unclassifed Manufacturers – 32-BIT MICROCONTROLLER

M0564
6.16 Serial Peripheral Interface (SPI)
6.16.1 Overview
The Serial Peripheral Interface (SPI) applies to synchronous serial data communication and
allows full duplex transfer. Devices communicate in Master/Slave mode with the 4-wire bi-
direction interface. The M0564 series contains up to two sets of SPI controllers performing a
serial-to-parallel conversion on data received from a peripheral device, and a parallel-to-serial
conversion on data transmitted to a peripheral device. Each SPI controller can be configured as a
master or a slave device.
This controller also supports the PDMA function to access the data buffer. The SPI controller also
support I²S mode to connect external audio CODEC.
6.16.2 Features
 SPI Mode
– Up to two sets of SPI controllers
– Supports Master or Slave mode operation
– Configurable bit length of a transaction word from 8 to 32-bit
– Provides separate 4-level depth transmit and receive FIFO buffers
– Supports MSB first or LSB first transfer sequence
– Supports Byte Reorder function
– Supports PDMA transfer
– Supports one data channel half-duplex transfer
– Support receive-only mode
 I²S Mode
– Supports Master or Slave
– Capable of handling 8-, 16-, 24- and 32-bit word sizes
– Provides separate 4-level depth transmit and receive FIFO buffers
– Supports monaural and stereo audio data
– Supports PCM mode A, PCM mode B, I²S and MSB justified data format
– Supports PDMA transfer
6.16.3 Timing Diagram
The active state of slave selection signal can be defined by setting the SSACTPOL
(SPIx_SSCTL[2]). The SPI clock which is in idle state can be configured as high or low state by
setting the CLKPOL (SPIx_CTL[3]). It also provides the bit length of a transaction word in
DWIDTH (SPIx_CTL[12:8]), and transmitting/receiving data from MSB or LSB first in LSB
(SPIx_CTL[13]). User can also select which edge of SPI clock to transmit/receive data in
TXNEG/RXNEG (SPIx_CTL[2:1]). Four SPI timing diagrams for master/slave operations and the
related settings are shown below.
May 05, 2017
Page 101 of 161
Rev 1.00