M0564LE4AE Datasheet, PDF (14/161 Pages) List of Unclassifed Manufacturers – 32-BIT MICROCONTROLLER

M0564
 PWM counter match zero, period value or compared value
– Supports up to 12 capture input channels with 16-bit resolution
– Supports rising or falling capture condition
– Supports input rising/falling capture interrupt
– Supports rising/falling capture with counter reload option
 USCI
USCI
– Supports up to 3 sets of USCI
UART Mode
SPI Mode
I²C Mode
USCI_CLK
-
SPI_CLK
SCL
USCI_CTL0
nCTS
SPI_SS
-
USCI_CTL1
nRTS
-
-
USCI_DAT0
Rx
SPI_MOSI
SDA
USCI_DAT1
Tx
SPI_MISO
-
– UART Mode
 Supports one transmit buffer and two receive buffer for data payload
 Supports hardware auto flow control function
 Supports programmable baud-rate generator
 Support 9-Bit Data Transfer (Support 9-Bit RS-485)
 Baud rate detection possible by built-in capture event of baud rate generator
 Supports Wake-up function (Data and nCTS Wakeup Only)
– SPI Mode
 Supports Master or Slave mode operation (the maximum frequency -- Master =
fPCLK / 2, Slave = fPCLK / 5)
 Supports one transmit buffer and two receive buffers for data payload
 Configurable bit length of a transfer word from 4 to 16-bit
 Supports MSB first or LSB first transfer sequence
 Supports Word Suspend function
 Supports 3-wire, no slave select signal, bi-direction interface
 Supports wake-up function by slave select signal in Slave mode
 Supports one data channel half-duplex transfer
– I²C Mode
 Full master and slave device capability
 Supports of 7-bit addressing, as well as 10-bit addressing
 Communication in standard mode (100 kBit/s) or in fast mode (up to 400 kBit/s)
 Supports multi-master bus
 Supports one transmit buffer and two receive buffer for data payload
 Supports 10-bit bus time-out capability
 Supports bus monitor mode.
 Supports Power down wake-up by data toggle or address match
 Supports setup/hold time programmable
 Supports multiple address recognition (two slave address with mask option)
 UART
– Supports up to 3 sets of UART
– Full-duplex asynchronous communications
– Separates receive and transmit 16/16 bytes entry FIFO for data payloads
– Supports hardware auto-flow control (RX, TX, CTS and RTS)
– Programmable receiver buffer trigger level
– Supports programmable baud rate generator for each channel individually
– Supports 8-bit receiver buffer time-out detection function
– Programmable transmitting data delay time between the last stop and the next start bit
by setting DLY (UART_TOUT [15:8])
May 05, 2017
Page 14 of 161
Rev 1.00