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M0564LE4AE Datasheet, PDF (77/161 Pages) List of Unclassifed Manufacturers – 32-BIT MICROCONTROLLER | |||
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M0564
6.2.12 Nested Vectored Interrupt Controller (NVIC)
The Cortex® -M0 provides an interrupt controller as an integral part of the exception mode, named
as âNested Vectored Interrupt Controller (NVIC)â, which is closely coupled to the processor kernel
and provides following features:
ï¬ Nested and Vectored interrupt support
ï¬ Automatic processor state saving and restoration
ï¬ Reduced and deterministic interrupt latency
The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in âHandler
Modeâ. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority.
All of the interrupts and most of the system exceptions can be configured to different priority
levels. When an interrupt occurs, the NVIC will compare the priority of the new interrupt to the
current running oneâs priority. If the priority of the new interrupt is higher than the current one, the
new interrupt handler will override the current handler.
When an interrupt is accepted, the starting address of the interrupt service routine (ISR) is fetched
from a vector table in memory. There is no need to determine which interrupt is accepted and
branch to the starting address of the correlated ISR by software. While the starting address is
fetched, NVIC will also automatically save processor state including the registers âPC, PSR, LR,
R0~R3, R12â to the stack. At the end of the ISR, the NVIC will restore the mentioned registers
from stack and resume the normal execution. Thus it will take less and deterministic time to
process the interrupt request.
The NVIC supports âTail Chainingâ which handles back-to-back interrupts efficiently without the
overhead of states saving and restoration and therefore reduces delay time in switching to
pending ISR at the end of current ISR. The NVIC also supports âLate Arrivalâ which improves the
efficiency of concurrent ISRs. When a higher priority interrupt request occurs before the current
ISR starts to execute (at the stage of state saving and starting address fetching), the NVIC will
give priority to the higher one without delay penalty. Thus it advances the real-time capability.
For more detailed information, please refer to the âARM® Cortex® -M0 Technical Reference
Manualâ and âARM® v6-M Architecture Reference Manualâ.
6.2.12.1 Exception Model and System Interrupt Map
Table 6.2-6 lists the exception model supported by the M0564 series. Software can set four levels
of priority on some of these exceptions as well as on all interrupts. The highest user-configurable
priority is denoted as â0â and the lowest priority is denoted as â3â. The default priority of all the
user-configurable interrupts is â0â. Note that priority â0â is treated as the fourth priority on the
system, after three system exceptions âResetâ, âNMIâ and âHard Faultâ.
Exception Type
Reset
NMI
Hard Fault
Reserved
SVCall
Reserved
PendSV
May 05, 2017
Vector Number
1
2
3
4 ~ 10
11
12 ~ 13
14
Vector Address
0x00000004
0x00000008
0x0000000C
0x0000002C
0x00000038
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Priority
-3
-2
-1
Reserved
Configurable
Reserved
Configurable
Rev 1.00
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