M0564LE4AE Datasheet, PDF (105/161 Pages) List of Unclassifed Manufacturers – 32-BIT MICROCONTROLLER

M0564
 Data bit is latched on positive edge of SPI bus clock.
 Data bit is driven on negative edge of SPI bus clock.
 Data is transferred from LSB first.
 SPI bus clock is idle at high state.
 Only one byte of data to be transmitted/received in a transaction.
 Slave selection signal is active high.
The operation flow is as follows:
1) Write the SPIx_SSCTL register a proper value for the related settings of Slave mode.
Select high level for the input of slave selection signal by setting SSACTPOL
(SPIx_SSCTL[2]) to 1.
2) Write the related settings into the SPIx_CTL register to control this SPI slave actions
1. Set the SPI controller as slave device by setting SLAVE (SPIx_CTL[18]) to 1.
2. Select the SPI clock idle state at high by setting CLKPOL (SPIx_CTL[3]) to 1.
3. Select data transmitted on negative edge of SPI bus clock by setting TXNEG
(SPIx_CTL[2]) to 1.
4. Select data latched on positive edge of SPI bus clock by clearing RXNEG (SPIx_CTL[1])
to 0.
5. Set the bit length of a transaction as 8-bit in DWIDTH bit field (SPIx_CTL[12:8] = 0x08).
6. Set LSB transfer first by setting LSB (SPIx_CTL[13]) to 1.
3) Set the SPIEN (SPIx_CTL[0]) to 1. Wait for the slave select trigger input and SPI clock input
from the off-chip master device to start the data transfer.
4) If this SPI slave attempts to transmit (be read) one byte data to the off-chip master device,
write the byte data that will be transmitted into the SPIx_TX register.
5) If this SPI slave just only attempts to receive (be written) one byte data from the off-chip
master device and does not care what data will be transmitted, the SPIx_TX register does not
need to be updated by software.
6) Waiting for SPI interrupt if the UNITIEN (SPIx_CTL[17]) is set to 1, or just polling the unit
transfer interrupt flag UNITIF (SPIx_STATUS[1]).
7) Read out the received one byte data from SPIx_RX register.
8) Go to 4) to continue another data transfer or stop data transfer.
May 05, 2017
Page 105 of 161
Rev 1.00