M0564LE4AE Datasheet, PDF (115/161 Pages) List of Unclassifed Manufacturers – 32-BIT MICROCONTROLLER

M0564
PWM period PWM period
CMPU = L
Zero = H
4
4
3
3
2
2
1
1
0
0
CMPDAT=0, 0% Duty
CMPDAT=1, 20% Duty
CMPDAT=2, 40% Duty
CMPDAT=3, 60% Duty
CMPDAT=4, 80% Duty
CMPDAT>4,100% Duty
PWM period
PWM period
CMPU = L
CMPD = H
4
4
33
33
2
2
2
2
1
11
1
0
0
0
CMPDAT=0, 0% Duty
CMPDAT=1, 25% Duty
CMPDAT=2, 50% Duty
CMPDAT=3, 75% Duty
CMPDAT=4, 100% Duty
Figure 6.17-9 PWM 0% to 100% Duty Cycle in Up Count Type and Up-Down Count Type
6.17.3.11 PWM Output Mode
The PWM supports two output modes: independent mode which may be applied to DC motor
system, complementary mode with dead-time insertion which may be used in the application of
AC induction motor and permanent magnet synchronous motor.
6.17.3.12 Independent mode
When OUTMODE (TIMERx_PWMCTL[16]) bit is set to 0, PWM output operates in independent
mode. In this mode, both PWMx_CH0 and PWMx_CH1 can output the same waveform as shown
in Figure 6.17-10.
PWMx_CH0
PWMx_CH1
Figure 6.17-10 PWM Independent Mode Output Waveform
6.17.3.13 Complementary mode
When OUTMODE (TIMERx_PWMCTL[16]) bit is set to 1, PWM output operates in
complementary mode. In this mode, both PWMx_CH0 and PWMx_CH1 can output waveform and
PWMx_CH1 must always be the complement of PWMx_CH0 as shown in Figure 6.17-11.
PWMx_CH0
PWMx_CH1
Figure 6.17-11 PWM Complementary Mode Output Waveform
6.17.3.14 PWM Output Control
After PWM pulse generator, there are four steps to control output waveform in independent output
mode and five control steps in complementary output mode. User can set POEN0
(TIMERx_PWMPOEN[0]) and POEN1 (TIMERx_PWMPOEN[1]) 1 to enable PWMx_CH0 and
PWMx_CH1 output waveform.
May 05, 2017
Page 115 of 161
Rev 1.00