M0564LE4AE Datasheet, PDF (84/161 Pages) List of Unclassifed Manufacturers – 32-BIT MICROCONTROLLER

M0564
6.3.2 System Clock and SysTick Clock
The system clock has 6 clock sources, which were generated from clock generator block. The
clock source switch depends on the register HCLKSEL (CLK_CLKSEL0 [2:0]). The block diagram
is shown in Figure 6.3-3.
HCLKSEL (CLK_CLKSEL0[2:0])
HIRC
LIRC
111111
001111
PLLFOUT
LXT
001100
000011
HXT
HIRC48
000000
110000
11//((HHCCLLKK_DNIV++11) )
CPUCLK
CPU
HCLK
AHB
HCLKDIV (CLK_CLKDIV0[3:0])
CPU in Power Down Mode
1/2 11
00
APB
Note: Before clock switching, both the pre-selected and newly selected clock source must be turned on and stable.
Figure 6.3-3 System Clock Block Diagram
There are two clock fail detectors to observe HXT and LXT clock source and they have individual
enable and interrupt control. When HXT detector is enabled, the HIRC clock is enabled
automatically. When LXT detector is enabled, the LIRC clock is enabled automatically.
When HXT clock detector is enabled, the system clock will auto switch to HIRC if HXT clock stop
being detected on the following condition: system clock source comes from HXT or system clock
source comes from PLL with HXT as the input of PLL. If HXT clock stop condition is detected, the
HXTFIF (CLK_CLKDSTS[0]) is set to 1 and chip will enter interrupt if HXTFIEN
(CLK_CLKDCTL[5]) is set to 1. User can trying to recover HXT by disable HXT and enable HXT
again to check if the clock stable bit is set to 1 or not. If HXT clock stable bit is set to 1, it means
HXT is recover to oscillate after re-enable action and user can switch system clock to HXT again.
The HXT clock stop detect and system clock switch to HIRC procedure is shown in Figure 6.3-4.
May 05, 2017
Page 84 of 161
Rev 1.00