M0564LE4AE Datasheet, PDF (86/161 Pages) List of Unclassifed Manufacturers – 32-BIT MICROCONTROLLER

M0564
6.3.4 Power-down Mode Clock
When entering Power-down mode, system clocks, some clock sources, and some peripheral
clocks are disabled. Some clock sources and peripherals clock are still active in Power-down
mode.
For theses clocks, which still keep active, are listed below:
 Clock Generator
– 10 kHz internal low-speed RC oscillator (LIRC) clock
– 32.768 kHz external low-speed crystal oscillator (LXT) clock
 Peripherals Clock (When the modules adopt LXT or LIRC as clock source)
6.3.5 Clock Output
This device is equipped with a power-of-2 frequency divider which is composed by16 chained
divide-by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one
multiplexer is reflected to CLKO function pin. Therefore there are 16 options of power-of-2 divided
clocks with the frequency from F_in/2¹ to F_in/2¹⁶ where F_in is input clock frequency to the clock
divider.
The output formula is F_out = F_in/2^(N+1), where F_in is the input clock frequency, F_out is the clock
divider output frequency and N is the 4-bit value in FREQSEL (CLK_CLKOCTL[3:0]).
When writing 1 to CLKOEN (CLK_CLKOCTL[4]), the chained counter starts to count. When
writing 0 to CLKOEN (CLK_CLKOCTL[4]), the chained counter continuously runs till divided clock
reaches low state and stay in low state.
if DIVI1EN(CLK_CLKOCTL[5]) set to 1, the clock output clock (CLKO_CLK) will bypass power-of-
2 frequency divider. The clock output clock will be output to CLKO pin directly.
CLKOSEL (CLK_CLKSEL2[4:2])
HIRC
011
HCLK
010
LXT
001
HXT
000
HIRC48
101
CLKOCKEN (CLK_APBCLK0[6])
CLKO_CLK
Note: Before clock switching, both the pre-selected and newly selected clock source must be turned on and stable.
Figure 6.3-6 Clock Source of Clock Output
May 05, 2017
Page 86 of 161
Rev 1.00