M0564LE4AE Datasheet, PDF (129/161 Pages) List of Unclassifed Manufacturers – 32-BIT MICROCONTROLLER

M0564
6.21 USCI - I²C Mode
6.21.1 Overview
On I²C bus, data is transferred between a Master and a Slave. Data bits transfer on the SCL and
SDA lines are synchronously on a byte-by-byte basis. Each data byte is 8-bit. There is one SCL
clock pulse for each data bit with the MSB being transmitted first, and an acknowledge bit follows
each transferred byte. Each bit is sampled during the high period of SCL; therefore, the SDA line
may be changed only during the low period of SCL and must be held stable during the high period
of SCL. A transition on the SDA line while SCL is high is interpreted as a command (START or
STOP). Please refer to Figure 6.21-1 for more detailed I²C BUS Timing.
STOP START
Repeated
START
STOP
SDA
SCL
t_BUF
t_LOW
t_r
t_f
t_{HD_STA}
t_HIGH
t_{HD_DAT}
t_{SU_DAT}
Figure 6.21-1 I²C Bus Timing
t_{SU_STA}
t_{SU_STO}
The device’s on-chip I²C provides the serial interface that meets the I²C bus standard mode
specification. The I²C port handles byte transfers autonomously. The I²C mode is selected by
FUNMODE (UI2C_CTL [2:0]) = 100b. When enable this port, the USCI interfaces to the I²C bus
via two pins: SDA and SCL. When I/O pins are used as I²C ports, user must set the pins function
to I²C in advance.
Note: Pull-up resistor is needed for I²C operation because the SDA and SCL are set to open-
drain pins when USCI is selected to I²C operation mode .
6.21.2 Features
 Full master and slave device capability
 Supports of 7-bit addressing, as well as 10-bit addressing
 Communication in standard mode (100 kBit/s) or in fast mode (up to 400 kBit/s)
 Supports multi-master bus
 Supports 10-bit bus time-out capability
 Supports bus monitor mode.
 Supports Power down wake-up by data toggle or address match
 Supports setup/hold time programmable
 Supports multiple address recognition (two slave address with mask option)
May 05, 2017
Page 129 of 161
Rev 1.00