M0564LE4AE Datasheet, PDF (79/161 Pages) List of Unclassifed Manufacturers – 32-BIT MICROCONTROLLER

M0564
42
26
43
27
44
28
45
29
46
30
47
31
PDMA_INT
PWRWU_INT
ADC_INT
CLKDIRC_INT
RTC_INT
PDMA interrupt
Reserved
Clock controller interrupt for chip wake-up from Power-down state
ADC interrupt
Clock fail detect and IRC TRIM interrupt
Real Time Clock interrupt
Table 6.2-7 Interrupt Number Table
6.2.12.2 Operation Description
NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-
Enable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-
1-to-clear policy, both registers reading back the current enabled state of the corresponding
interrupts. When an interrupt is disabled, interrupt assertion will cause the interrupt to become
Pending, however, the interrupt will not activate. If an interrupt is Active when it is disabled, it
remains in its Active state until cleared by reset or an exception return. Clearing the enable bit
prevents new activations of the associated interrupt.
NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used
to enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register
respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers
reading back the current pended state of the corresponding interrupts. The Clear-Pending
Register has no effect on the execution status of an Active interrupt.
NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register
supporting four interrupts).
The general registers associated with the NVIC are all accessible from a block of memory in the
System Control Space and will be described in next section.
May 05, 2017
Page 79 of 161
Rev 1.00