M0564LE4AE Datasheet, PDF (81/161 Pages) List of Unclassifed Manufacturers – 32-BIT MICROCONTROLLER

M0564
6.3 Clock Controller
6.3.1 Overview
The clock controller generates clocks for the whole chip, including system clocks and all
peripheral clocks. The clock controller also implements the power control function with the
individually clock ON/OFF control, clock source selection and a clock divider. The chip will not
enter Power-down mode until CPU sets the Power-down enable bit PDEN(CLK_PWRCTL[7]) and
Cortex^® -M0 core executes the WFI instruction. After that, chip enters Power-down mode and wait
for wake-up interrupt source triggered to leave Power-down mode. In Power-down mode, the
clock controller turns off the 4~24 MHz external high speed crystal (HXT), internal 22.1184 MHz
internal high speed RC oscillator (HIRC) and 48 MHz internal high speed RC oscillator (HIRC48)
to reduce the overall system power consumption. Figure 6.3-1 shows the clock generator and the
overview of the clock source control.
The clock generator consists of 6 clock sources, which are listed below:
 32.768 kHz external low-speed crystal oscillator (LXT)
 4~24 MHz external high speed crystal oscillator (HXT)
 Programmable PLL output clock frequency (PLLFOUT), PLL source can be selected
from external 4~24 MHz external high speed crystal (HXT) or 22.1184 MHz internal
high speed oscillator (HIRC)
 22.1184 MHz internal high speed RC oscillator (HIRC)
 48 MHz internal high speed RC oscillator (HIRC48)
 10 kHz internal low speed RC oscillator (LIRC)
Each of these clock sources has certain stable time to wait for clock operating at stable
frequency. When clock source is enabled, a stable counter start counting and correlated clock
stable
index
(HIRCSTB(CLK_STATUS[4]),
LIRCSTB(CLK_STATUS[3]),
PLLSTB(CLK_STATUS[2]), HXTSTB(CLK_STATUS[0]), LXTSTB(CLK_STATUS[1]) and
HIRC48STB(CLK_STATUS[5])) are set to 1 after stable counter value reach a define value as
shown in Table 6.3-8. System and peripheral can use the clock as its operating clock only when
correlate clock stable index is set to 1. The clock stable index will auto clear when user disables
the
clock
source
(LIRCEN(CLK_PWRCTL[3]),
HIRCEN(CLK_PWRCTL[2]),
HXTEN(CLK_PWRCTL[0]),
PD(CLK_PLLCTL[16]), LXTEN(CLK_PWRCTL[1]) and
HIRC48EN(CLK_PWRCTL[13])). Besides, the clock stable index of HXT, HIRC and PLL will auto
clear when chip enter power-down and clock stable counter will re-counting after chip wake-up if
correlate clock is enabled.
May 05, 2017
Page 81 of 161
Rev 1.00