M0564LE4AE Datasheet, PDF (111/161 Pages) List of Unclassifed Manufacturers – 32-BIT MICROCONTROLLER

M0564
CNT
(TIMERx_PWMCNT[15:0])
DIRF
(TIMERx_PWMCNT[16])
Up-count compared
point event (CMPU)
Down-count compared
point event (CMPD)
PERIOD = 4
CMPDAT = 4
PERIOD = 7
CMPDAT = 5
PERIOD = 5
CMPDAT= 0
012343210123456765432101234
PWM Period
PWM Period
Note: No CMPU event occurred when CMPDAT equals to PERIOD.
Figure 6.17-5 PWM Comparator Events in Up-Down Count Type
6.17.3.8 Period Loading Mode
When the IMMLDEN (TIMERx_PWMCTL[9]) bit set to 0, PWM operates at period loading mode.
The PWM provides PBUF (TIMERx_PWMPBUF[15:0]) is the active PERIOD buffer register and
CMPBUF (TIMERx_PWMCMPBUF[15:0]) is the active CMP buffer register. In period loading
mode, both PERIOD (TIMERx_PWMPERIOD[15:0]) and CMP (TIMERx_PWMCMPDAT[15:0])
will load to their active PBUF and CMPBU register while each PWM period is completed. Figure
6.17-6 shows period loading timing of up count type, where PERIOD DATA0 denotes the initial
data of PERIOD, PERIOD DATA1 denotes the first updated PERIOD data by user and so on,
CMP also follows this rule. The following steps are the sequence of Figure 6.17-6.
1. User writes CMP DATA1 to CMPDAT at point 1.
2. Period loading CMP DATA1 to CMPBUF at the end of PWM period at point 2.
3. User writes PERIOD DATA1 to PERIOD at point 3.
4. Period loading PERIOD DATA1 to PBUF at the end of PWM period at point 4.
5. User writes PERIOD DATA2 to PERIOD at point 5.
6. Period loading PERIOD DATA2 to PBUF at the end of PWM period at point 6.
May 05, 2017
Page 111 of 161
Rev 1.00