M32L1632512A Datasheet, PDF (9/54 Pages) List of Unclassifed Manufacturers – 256K x 32 Bit x 2 Banks Synchronous Graphic RAM

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M32L1632512A
SIMPLIFIED TRUTH TABLE
COMMAND
CKEn-1 CKEn _{CS RAS CAS WE} DSF DQM A10 A9 A8~A0 Note
Register
Refresh
Mode Register set
H
Special Mode Register Set
Auto Refresh
H
Entry
Self
Refresh
Exit
L
Bank Active ^{Write Per Bit Disable}
& Row Addr. _{Write Per Bit Enable}
H
XLL L L ^L X
H
H
LL L H L X
L
OP CODE
X
1, 2
1, 2, 7
3
3
LH H H
3
H
XX
X
HX X X
3
L
4, 5
XLL H H
X V Row Address
H
4,5,9
Read & Column ^{Auto Precharge Disable}
Address
Auto Precharge Enable
Write & Column ^{Auto Precharge Disable}
Address
Auto Precharge Enable
Block Write & ^{Auto Precharge Disable}
Column Address _{Auto Precharge Enable}
Burst Stop
H
X LH
L
H
L
X
V
L
H
Column
Address
4
4, 6
H
X LH
L
L
L
X
V
L
H
Column 4, 5
Address _4,5,6,9
H
X LH
L
L
H
X
V
L
H
Column 4, 5
Address _4,5,6,9
H X LH H L L X
X
7
Precharge
Bank Selection
Both Banks
VL
H XLL H L L X
X
XH
Clock Suspend or
Active Power Down
LH H H
Entry H
L
XX
HX X X
X
Exit
L
HXX X X X X
LH H H
Entry H
L
XX
Precharge Power Down Mode
HX X X
X
LV V V V
Exit
L
H _{HX X X X} ^X
DQM
No Operation Command
H
X
V
X
8
LH H H
HX
XX
X
HX X X
(V = Valid, X = Don’t Care. H = Logic High, L = Logic Low )
Note : 1.OP Code : Operand Code
A0~A10 : Program keys. (@ MRS)
A5, A6 : LMR & LCR select. (@ SMRS)
Color register exists only one per DQi which both banks share.
So does Mask Register.
Color or mask is loaded into chip through DQ pin.
2.MRS can be issued only at both banks precharge state.
SMRS can be issued only if DQ’s are idle.
A new command can be issued at the next clock of MRS/SMRS.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6
9/54