M32L1632512A Datasheet, PDF (24/54 Pages) List of Unclassifed Manufacturers – 256K x 32 Bit x 2 Banks Synchronous Graphic RAM

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M32L1632512A
3) Read (BL=4)
CLK
CMD
RD
DQ(CL2)
DQ(CL3)
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
*Note3
Auto Precharge starts
*Note : 1. tRDL : Write data-in to PRE command delay, tBPL : Block Write data-in to PRE command delay.
2. Number of valid output data after row precharge : 1, 2 for CAS Latency = 2, 3 respectively.
3. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of other activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same bank is illegal.
4. For -5S/-6S/-7S/-8S, auto precharge after a normal write starts at clock(n+BL+1).
8. Burst Stop & Precharge Interrupted
1) Write interrupted by Precharge (BL=4)
2) Write Burst Stop (Full Page Only)
CLK
CLK
CMD
WR
PRE
CMD
WR
STOP
DQM
DQ
D0 D1 D2 D3
t *Note1
RDL
3) Read interrupted by Precharge (BL=4)
DQ
D0 D1 D2
tB DL
4) Read Burst Stop (Full Page Only)
CLK
CLK
CMD
RD
DQ(CL2)
DQ( C L3 )
PRE
Q0
* Note 3
1
Q1
CMD
RD
STOP
DQ(CL2)
*Note 3
1
Q0 Q1
2
Q0 Q1
DQ(CL3)
2
Q0 Q1
9. MRS & SMRS
1) Mode Register Set
CLK
CMD
*Note4
PRE
tRP
MRS ACT
1CLK
Elite Semiconductor Memory Technology Inc.
2) Special Mode Register Set
CLK
CMD
SMRS ACT SMRSSMRS ACT
1CLK 1CLK 1CLK 1CLK
Publication Date : Jun. 2001
Revision : 1.6
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