M32L1632512A Datasheet, PDF (36/54 Pages) List of Unclassifed Manufacturers – 256K x 32 Bit x 2 Banks Synchronous Graphic RAM

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M32L1632512A
Read & Write Cycle at Same Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10 11 12 13
14 15 16 17 18 19
CLOCK
CKE
CS
RAS
CAS
tRC D
*Note1
tRC
HIGH
*Not e2
ADDR
Ra
Ca0
Rb
Cb0
A1 0
A9
Ra
Rb
WE
DSF
DQM
DQ CL=2
CL = 3
tR AC
*Not e 3
tRAC
*Note3
tOH
Qa0 Qa1 Qa2 Qa3
tSAC
Q a0
tO H
Qa1
Qa2
tSHZ ^*Note4
Q a3
tS AC
t *Note4
SHZ
Db0 Db1 Db2 Db3
tRDL
Db0 Db1 Db2 Db3
tRDL
Row Active
(A-Bank)
R ea d
(A- Ban k)
Precharge
( A-Bank)
Row Active
( A- Bank )
W rite
(A-Bank)
Precharge
(A-Ban k)
*Note :
1. Minimum row cycle time is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle.[CAS Length - 1] valid output data available after Row. enters
t Hi-Z after SHZ from the clock.
t t t 3. Access time from Row address. CC *( RCD +CAS latency - 1) + SAC
4. Output will be Hi-Z after the end of burst. (1, 2, 4 & 8)
At Full page bit burst, burst is wrap-around.
:Don't Care
precharge. Last valid output will be
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6
36/54