M32L1632512A Datasheet, PDF (7/54 Pages) List of Unclassifed Manufacturers – 256K x 32 Bit x 2 Banks Synchronous Graphic RAM

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M32L1632512A
*Note : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2 - 0.5) ns should be added to the parameter.
3. Assumed input rising and falling time (tr & tf) = 1ns.
If tr & tf is longer 1ns, transient time compensation should be considered.
i.e., [(tr + tf)/2 - 1] ns should be added to the parameter.
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
Row active to row active delay
RAS to CAS delay
Row precharge time
tRRD(min)
tRCD(min)
tRP(min)
Row active time
Row cycle time
Last data in to new col. address delay
Last data in to row precharge
Block write data-in to PRE command delay
Block write data-in to Active (REF)
command period (Auto precharge)
Last data to burst stop
Col. Address to col. Address delay
Block write cycle time
tRAS(min)
tRAS(max)
tRC(min)
tCDL(min)
tRDL(min)
tBPL(min)
tBAL(min)
tBDL(min)
tCCD(min)
tBWC(min)
Number of valid Output data
CAS latency = 3
CAS latency = 2
-5 -5S
10
15
15
40
55
12
10
25
2
Version
Unit
-6 -6S -7 -7S -8 -8S
12
14
16
18
20
20
ns
18
21
24
ns
40
42
48
ns
100
us
60
63
72
ns
1
CLK
1 2 1 2 1 2 CLK
12
14
16
ns
30
35
40
ns
1
1
2
2
2
1
CLK
CLK
2
CLK
CLK
Note
1
1
1
1
1
2
2
2
3
4
5
Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with
clock cycle time and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change except block write cycle.
4. This parameter means minimum CAS to CAS delay at block write cycle only.
5. In case of row precharge interrupt, auto precharge and read burst stop.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6
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