M32L1632512A Datasheet, PDF (4/54 Pages) List of Unclassifed Manufacturers – 256K x 32 Bit x 2 Banks Synchronous Graphic RAM

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M32L1632512A
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V)
Parameter
Symbol
Min
Supply voltage
VDD, VDDQ
3.0
Input high voltage
VIH
2.0
Input low voltage
VIL
-0.3
Output high voltage
VOH
2.4
Output low voltage
VOL
-
Input leakage current
IIL
-5
Output leakage current
IOL
-5
Output Loading Condition
Typ
Max
Unit
3.3
3.6
V
3.0
VDD+0.3
V
0
0.8
V
-
-
V
-
0.4
V
-
5
µÂ
-
5
µÂ
See Fig 1
Note: 1. VIL(min) = -1.5V AC (pulse width ≤ 5ns)
2. Any input 0V ≤ VIN ≤ VDD + 0.3V, all other pins are not under test = 0V.
4. Dout is disabled, 0V ≤ VOUT ≤ VDD.
Note
Note 1
IOH = -2mA
IOL = 2mA
Note 2
Note 3
CAPACITANCE (VDD/VDDQ = 3.3V, TA = 25 °C , f = 1MHZ)
Parameter
Symbol
Min
Max
Unit
Input capacitance (A0 ~ A10)
CIN1
-
4
pF
Input capacitance
CIN2
-
(CLK, CKE, CS , RAS , CAS , WE , DSF& DQM0-3)
4
pF
Data input/output capacitance (DQ0 ~ DQ31)
COUT
-
5
pF
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitance added to power line at board.
Parameter
Decoupling Capacitance between VDD & VSS
Decoupling Capacitance between VDDQ & VSSQ
Symbol
Value
Unit
CDC1
0.1+0.01
uF
CDC2
0.1+0.01
uF
*Note: 1. VDD and VDDQ pins are separated each other.
All VDD pins are connected in chip. All VDDQ pins are connected in chip.
2. VSS and VSSQ pins are separated each other.
All VSS pins are connected in chip. All VSSQ pins are connected in chip.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6
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