M32L1632512A Datasheet, PDF (30/54 Pages) List of Unclassifed Manufacturers – 256K x 32 Bit x 2 Banks Synchronous Graphic RAM

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M32L1632512A
FUNCTION TRUTH TABLE (TABLE 1)
Current
State
IDLE
Row
Active
Read
Write
CS RAS CAS WE DSF
HX
LH
LH
LH
LL
LL
LL
LL
LL
LL
LL
LL
HX
LH
LH
LH
LH
LH
LH
LL
LL
LL
LL
LL
LL
HX
LH
LH
LH
LH
LH
LH
LH
LL
LL
LL
LL
HX
LH
LH
LH
LH
LH
LH
LH
XXX
HHX
HLX
LXX
HHL
HHH
HLL
HLH
LHL
L HH
LLL
L LH
XXX
HHX
HLX
LHL
L HH
LLL
L LH
HHX
HLL
HLH
L HX
LLL
L LH
XXX
HHX
HLL
HLH
LHL
L HH
LLL
L LH
HHX
HLL
HLH
LXX
XXX
HHX
HLL
HLH
LHL
L HH
LLL
L LH
BA
(A10)
ADDR
X
X
X
X
X
X
BA
CA
BA
RA
BA
RA
X
PA
BA
X
X
X
BA
X
OP Code
OP Code
X
X
X
X
X
X
BA CA, AP
X
X
BA CA, AP
BA CA, AP
BA
RA
BA
RA
X
X
X
X
X
X
OP Code
X
X
X
X
X
X
X
X
BA CA, AP
X
X
BA CA, AP
BA CA, AP
BA
RA
BA
PA
X
X
X
X
X
X
X
X
X
X
X
X
BA CA, AP
X
X
BA CA, AP
BA CA, AP
ACTION
Note
NOP
NOP
ILLEGAL
2
ILLEGAL
2
Row Active ; Latch Row Address ; Non-IO Mask
Row Active ; Latch Row Address ; IO Mask
Auto Refresh or Self Refresh
4
NOP
Auto Refresh or Self Refresh
5
ILLEGAL
Mode Register Access
5
Special Mode Register Access
6
NOP
NOP
ILLEGAL
2
Begin Read ; Latch CA ; Determine AP
ILLEGAL
Begin Write ; Latch CA ; Determine AP
Begin Write ; Latch CA ; Determine AP
ILLEGAL
2
Precharge
ILLEGAL
ILLEGAL
ILLEGAL
Special Mode Register Access
Æ NOP (Continue Burst to End
Æ NOP (Continue Burst to End
Æ Term burst Row active
Row Active)
Row Active)
6
ILLEGAL
Term burst, Begin Read ; Latch CA ; Determine AP 3
ILLEGAL
Term burst, Begin Write ; Latch CA ; Determine AP
3
Term burst, Begin Write ; Latch CA ; Determine AP
3
ILLEGAL
2
Term Burst, Precharge timing for Reads
3
ILLEGAL
ILLEGAL
Æ NOP (Continue Burst to End
Æ NOP (Continue Burst to End
Æ Term burst Row Active
Row Active)
Row Active)
ILLEGAL
Term burst, Begin Read ; Latch CA ; Determine AP 3
ILLEGAL
Term burst, Begin Write ; Latch CA ; Determine AP
3
Term burst, Begin Write ; Latch CA ; Determine AP
3
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6
30/54