M32L1632512A Datasheet, PDF (18/54 Pages) List of Unclassifed Manufacturers – 256K x 32 Bit x 2 Banks Synchronous Graphic RAM

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DEVICE OPERATIONS (Continued)
to be coupled into the internal color register. The
color register provides the data masked by the DQ
column select, WPB mask (if enable), and DQM
byte mask. Column data masking (Pixel masking) is
provided on an individual column basis for each
byte of data. The column mask is driven on the DQ
pins during a block write command. The DQ
column mask function is segmented on a per bit
basis (i.e. DQ [0:7] provided the column mask for
data bits [0:7], DQ [8:15] provided the column mask
for data bits [8:15], DQ0 masks column [0] for data
bits[0:7], DQ9 masks column [1] for data bits[8:15],
etc). Block writes are always non-burst independent
of the burst length that has been programmed into to
the mode register. If write per bit was enabled by the
bank active command with DSF=1, then write per
bit masking of the color register data is enabled.
If write per bit was disabled by a bank active
command with DSF=0, the write per bit masking of
the color register data is disabled. DQM masking
provides independent data byte masking during
normal write operations, except that the control is
extended to the consecutive 8 columns of the block
write.
M32L1632512A
Timing Diagram to Illustrate tBWC
1. 2CLK Cycle Block Write
CLOCK
CKE
CS
RAS
CAS
WE
DSF
HIGH
2 CLK BW
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6
18/54