M32L1632512A Datasheet, PDF (28/54 Pages) List of Unclassifed Manufacturers – 256K x 32 Bit x 2 Banks Synchronous Graphic RAM

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M32L1632512A
(Continued)
i) ILLUSTRATION
I/O (=DQ)
DQMi
Color Register
000
Before 001
Block ₀₁₀
Write
&
011
DQ
100
(Pixel
data)
101
110
111
After
Block
Write
000
001
010
011
100
101
110
111
Note 1
31
24
DQM3=0
Color3=Blue
White DQ24=H
White DQ25=H
White DQ26=H
White DQ27=L
White DQ28=H
White DQ29=H
White DQ30=H
White DQ31=L
Blue
Blue
Blue
White
Blue
Blue
Blue
White
23
16
DQM2=0
Color2=Green
White DQ16=H
White DQ17=H
White DQ18=L
White DQ19=H
White DQ20=H
White DQ21=H
White DQ22=L
White DQ23=H
Green
Green
White
Green
Green
Green
White
Green
15
8
DQM1=0
Color1=Yellow
White DQ8=H
White DQ9=L
White DQ10=H
White DQ11=H
White DQ12=H
White DQ13=L
White DQ14=H
White DQ15=H
Yellow
White
Yellow
Yellow
Yellow
White
Yellow
Yellow
7
0
DQM0=1
Color0=Red
White DQ0=L
White DQ1=H
White DQ2=H
White DQ3=H
White DQ4=L
White DQ5=H
White DQ6=H
White DQ7=H
White
White
White
White
White
White
White
White
Pixel and I/O masking : By Mask at Write Per Bit Mode, the selected bit planes keep the original data.
By Pixel Data issued through DQ pin, the selected pixels keep the original data.
See PIXEL TO DQ MAPPING TABLE.
Assume 8bpp,
White = “0000, 0000”, Red = “1010, 0011”, Green = “1110, 0001”, Yellow = “0000, 1111”, Blue = “1100, 0011”
i) STEP
I SMRS(LCR) : Load color (for 8bpp, through x 32 DQ color0-3 are loaded into color registers)
Load (color3, color2, color1, color0, ) = (Blue, Green, Yellow, Red)
=”1100, 0011, 1110, 0001, 0000, 1111, 1010, 0011”
ÆII SMRS(LMR) Load mask. Mask[31-0] = ”1111.1111. 1101, 1101, 0100, 0010, 0111, 0110”
Byte 3 : No I/O Masking ; Byte 2 : I/O Masking ; Byte 1 : I/O and Pixel Masking ; Byte 0 : DQM Byte Masking
III Row Active with DSF “H” : I/O mask by Write Per Bit Mode Enable
IV Block Write with DQ [31-0] = ”0111, 0111 .1111, 1111, 0101, 0101, 1110, 1110 ”(Pixel Mask)
*Note : 1. At normal write, ONE column is selected among columns decorded by A2-0 (000-111).
At block write, instead of ignored address A2-0, DQ0-31 control each pixel.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6
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