M32L1632512A Datasheet, PDF (49/54 Pages) List of Unclassifed Manufacturers – 256K x 32 Bit x 2 Banks Synchronous Graphic RAM

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M32L1632512A
Clock suspension & DQM operation cycle @ CAS Latency = 2, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11 12 13
14 15
16 17 18 19
CL OC K
CKE
CS
RAS
CAS
ADDR
Ra
Ca
Cb
Cc
A1 0
A9
RA
WE
DSF
DQM
*Note1
DQ
Row Active Read
Qa0 Qa1
Qa2
Q a3
tSHZ
Clock
S u s pen s i on
R ea d
Qb0 Qb1
tSHZ
Dc 0
Dc2
Read DQM
W ri te
DQ M
W r ite
Clock
Suspension
:Don't Care
*Note : 1. DQM needed to prevent bus contention.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6
49/54