M32L1632512A Datasheet, PDF (52/54 Pages) List of Unclassifed Manufacturers – 256K x 32 Bit x 2 Banks Synchronous Graphic RAM

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Mode Register Set Cycle
0
1
2
3
4
5
6
CLOCK
CKE
HIGH
CS
RAS
CAS
ADDR
*Note 2
*Note 1
*Note 3
Key Ra
WE
DSF
DQM
DQ
Hi-Z
MRS New
Command
M32L1632512A
Auto Refresh Cycle
0
1
2
3
4
5
6
7
8
9
10
HIGH
tR C
Hi-Z
Auto Refresh
New Command
:Don't Care
*Both bank precharge should be completed Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
*Note : 1. CS , RAS , CAS & WE activation and DSF of low at the same clock cycle with address key will set internal mode
register.
2. Minimum 1 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6
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