M32L1632512A Datasheet, PDF (15/54 Pages) List of Unclassifed Manufacturers – 256K x 32 Bit x 2 Banks Synchronous Graphic RAM

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M32L1632512A
DEVICE OPERATIONS (Continued)
active row in an active bank. The burst read
command is issued by asserting low on CS and
CAS with WE being high on the positive edge of
the clock. The bank must be active for at least tRCD
(min) before the burst read command is issued. The
first output appears in CAS latency number of
clock cycles after the issue of burst read command.
The burst length, burst sequence and latency from
the burst read command is determined by the mode
register which is already programmed. The burst
read can be initiated on any column address of the
active row. The address wraps around if the initial
address does not start from a boundary such that
number of outputs from each I/O are equal to the
burst length programmed in the mode register. The
output goes into high-impedance at the end of burst,
unless a new burst read was initiated to keep the
data output gapless. The burst read can be
terminated by issuing another burst read or burst
write in the same bank or the other active bank or a
precharge command to the same bank. The burst
stop command is valid for all burst length.
BURST WRITE
The burst write command is similar to burst read
command, and is used to write data into the
SGRAM on consecutive clock cycles in adjacent
addresses depending on burst length and burst
sequence. By asserting low on CS , CAS and
WE with valid column address, a write burst is
initiated. The data inputs are provided for the initial
address in the same clock cycle as the burst write
command. The input buffer is deselected at the end
of the burst length, even though the internal writing
may not have been completed yet. The writing can
not complete to burst length. The burst write can be
terminated by issuing a burst read and DQM for
blocking data inputs or burst write in the same or
the other active bank.
The write burst can also be terminated by using
DQM for blocking data and precharging the
bank “tRDL” after the last data input to be written
into the active row. See DQM OPERATION
also.
DQM OPERATION
The DQM is used mask input and output
operations. It works similar to OE during
operation and inhibits writing during write
operation. The read latency is two cycles from
DQM and zero cycle for write, which means
DQM masking occurs two cycles later in read
cycle and occurs in the same cycle during write
cycle. DQM operation is synchronous with the
clock. The DQM signal is important during
burst interrupts of write with read or precharge
in the SGRAM. Due to asynchronous nature of
the internal write, the DQM operation is critical
to avoid unwanted or incomplete writes when
the complete burst write is required. DQM is
also used for device selection and bus control in
a memory system. DQM0 controls DQ0 to
DQ7, DQM1 controls DQ8 to DQ15, DQM2
controls DQ16 to DQ23, DQM3 controls DQ24
to DQ31. DQM masks the DQ’s by a byte
regardless that the corresponding DQ’s are in a
state of WPB masking or Pixel masking. Please
refer to DQM timing diagram also.
PRECHARGE
The precharge is performed on an active bank
by asserting low on CS , RAS , WE and A9
with valid A10 of the bank to be precharged.
The precharge command can be asserted
anytime after tRAS (min) is satisfy from the bank
activate command in the desired bank. “tRP” is
defined as the minimum time required to
precharge a bank.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6
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