M32L1632512A Datasheet, PDF (35/54 Pages) List of Unclassifed Manufacturers – 256K x 32 Bit x 2 Banks Synchronous Graphic RAM

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M32L1632512A
* Note : 1. All input can be don’t care when CS is high at the CLK high going edge.
2. Bank active & read/write are controlled by A10.
A10
Active & Read/Write
0
Bank A
1
Bank B
3. Enable and disable auto precharge function are controlled by A9 in read/write command.
A9
A10
Operation
0
0
Disable auto precharge, leave bank A active at end of burst.
1
Disable auto precharge, leave bank B active at end of burst.
1
0
Enable auto precharge, precharge bank A at end of burst.
1
Enable auto precharge, precharge bank B at end of burst.
4. A9 and A10 control bank precharge when precharge command is asserted.
A9
A10
0
0
0
1
1
X
Precharge
Bank A
Bank B
Both Bank
5. Enable and disable Write-per Bit function are controlled by DSF in Row Active command.
A10 DSF
Operation
0
L Bank A row active, disable write per bit function for bank A.
H Bank A row active, enable write per bit function for bank A.
1
L Bank B row active, disable write per bit function for bank B.
H Bank B row active, enable write per bit function for bank B.
6. Block write/normal write is controlled by DSF.
DSF
Operation
L
Normal write
H
Block write
Minimum cycle time
tCCD
tBWC
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6
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