M32L1632512A Datasheet, PDF (20/54 Pages) List of Unclassifed Manufacturers – 256K x 32 Bit x 2 Banks Synchronous Graphic RAM

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2. DQM Operation
M32L1632512A
1)Write Mask (BL=4)
CLK
CMD
WR
DQM
DQ(CL2)
D0 D1
Maske d by DQM
D3
DQ(CL3)
D0 D1
D3
DQM to Data-in Mask=0 CLK
2)Read Mask (BL=4)
RD
Masked by DQM
Q0 ^Hi-Z Q2
Q3
Hi-Z
Q1 Q2 Q3
DQM to Data-out Mask=2
3)DQM with clcok suspended (Full Page Read)
Note2
CLK
CMD
RD
CKE
DQM
DQ(CL2)
DQ(CL3)
Hi-Z
Q0
Q2
H i- Z
Q1
H i- Z
Q4
Hi-Z
Q3
Hi-Z
Hi-Z
Q6 Q7 Q8
Q5 Q6 Q7
*Note : 1. There are 4 DQMi (i = 0~3).
Each DQMi masks 8 DQ’s. (1 Byte, 1 Pixel for 8bpp).
2. DQM masks data out Hi-Z after 2 clocks which should masked by CKE “L”.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6
20/54