M32L1632512A Datasheet, PDF (13/54 Pages) List of Unclassifed Manufacturers – 256K x 32 Bit x 2 Banks Synchronous Graphic RAM

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M32L1632512A
DEVICE OPERATIONS
CLOCK (CLK)
The clock input is used as the reference for all
SGRAM operations. All operations are
synchronized to the positive going edge of the
clock. The clock transitions must be monotonic
between VIL and VIH. During operation with CKE
high all inputs are assumed to be in valid state (low
or high) for the duration of setup and hold time
around positive edge of the clock for proper
functionality and Icc specifications.
CLOCK ENABLE(CKE)
The clock enable (CKE) gates the clock onto
SGRAM. If CKE goes low synchronously with
clock (set-up and hold time same as other inputs),
the internal clock suspended from the next clock
cycle and the state of output and burst address is
frozen as long as the CKE remains low. All other
inputs are ignored from the next clock cycle after
CKE goes low. When both banks are in the idle
state and CKE goes low synchronously with clock,
the SGRAM enters the power down mode from the
next clock cycle. The SGRAM remains in the
power down mode ignoring the other inputs as long
as CKE remains low. The power down exit is
synchronous as the internal clock is suspended.
When CKE goes high at least “tSS+1CLOCK”
before the high going edge of the clock, then the
SGRAM becomes active from the same clock edge
accepting all the input commands.
BANK SELECT (A10)
This SGRAM is organized as two independent
banks of 262, 144 words x 32 bits memory arrays.
The A10 inputs are latched at the time of assertion
of RAS and CAS to select the bank to be used
for the operation. When A10 is asserted low, bank
A is selected. When A10 is latched high, bank B is
selected. The banks select A10 is latched at bank
activate, read, write, mode register set and
precharge operations.
ADDRESS INPUTS (A0~A9)
The 18 address bits are required to decode the
262,144 word locations are multiplexed into 10
address input pins (A0~A9). The 10 bit row
address is latched along with RAS and A10
during bank activate command. The 8 bit
column address is latched along with CAS,
WE and A10 during read or write command.
NOP and DEVICE DESELECT
When RAS , CAS and WE are high, The
SGRAM performs no operation (NOP). NOP
does not initiate any new operation, but is
needed to complete operations which require
more than single clock cycle like bank activate,
burst read, auto refresh, etc. The device deselect
is also a NOP and is entered by asserting CS
high. CS high disables the command decoder
so that RAS , CAS, WE , DSF and all the
address inputs are ignored.
POWER-UP
The following sequence is recommended for
POWER UP
1.Power must be applied to either CKE and
DQM inputs to pull them high and other pins
are NOP condition at the inputs before or
along with VDD (and VDDQ) supply.
The clock signal must also be asserted at the
same time.
2.After VDD reaches the desired voltage, a
minimum pause of 200 microseconds is
required with inputs in NOP condition.
3.Both banks must be precharged now.
4.Perform a minimum of 2 Auto refresh cycles
to stabilize the internal circuitry.
5.Perform a MODE REGISTER SET cycle to
program the CAS latency, burst length and
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6
13/54