M32L1632512A Datasheet, PDF (11/54 Pages) List of Unclassifed Manufacturers – 256K x 32 Bit x 2 Banks Synchronous Graphic RAM

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M32L1632512A
Test Mode
A8 A7
Type
A6
0 0 Mode Register Set 0
01
Vendor
0
10
Use
0
11
Only
0
Write Burst Length
1
A9
Length
1
0
Burst
1
1
Single Bit
1
CAS Latency
Burst Type
A5 A4 Latency A3 Type A2
0 0 Reserved 0 Sequential 0
01
-
1 Interleave 0
10
2
0
11
3
0
0 0 Reserved
1
0 1 Reserved
1
1 0 Reserved
1
1 1 Reserved
1
Burst Length
A1 A0 BT = 0 BT = 1
00
1 Reserved
01
2 Reserved
10
4
4
11
8
8
0 0 Reserved Reserved
0 1 Reserved Reserved
1 0 Reserved Reserved
1 1 256(Full) Reserved
(Note 3)
Special Mode Register Programmed with SMRS
Address A10
A9
A8
A7
A6
A5
A4
Function
X
LC
LM
A3
A2
X
A1
A
POWER UP SEQUENCE
Load Color
A6 Function
0 Disable
1
Enable
Load Mask
A5 Function
0
Disable
1
Enable
(Note 4)
1.Apply power and start clock, Attempt to maintain CKE = ”H”, DQM = ”H” and the other pin are NOP
condition at the inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200 µ s.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 may be changed.
The device is now ready for normal operation.
Note : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.
2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.
3. The full column burst (256bit) is available only at Sequential mode of burst type.
4. If LC and LM both high (1), data of mask and color register will be unknown.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6
11/54