M32L1632512A Datasheet, PDF (48/54 Pages) List of Unclassifed Manufacturers – 256K x 32 Bit x 2 Banks Synchronous Graphic RAM

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M32L1632512A
Burst Read Single bit Write Cycle @ Burst Length = 2, BRSW
0
1
2
3
4
5
6
7
8
9
10 11 12 13
14 15 16 17 18 19
CLOCK
CKE
*Note 1
HIGH
CS
RAS
CAS
ADDR
RAa
CAa RBb CAb
*Note 2
RAb CBc
CAd
A1 0
A9
RAa
RBb
RAc
WE
DSF
DQM
CL=3
QAa0
QAa0
DAb0 DAb1
DBc0
DAb0 DAb1
D Bc 0
DAd0 DAd1
DAd0 DAd1
Row Active
(A-Ban k)
Row Active
( B- B an k )
W rit e
(A-Bank)
Read with
Auto Precharge
(A-Bank)
Row Active
( A- B an k )
Read
(A-Bank)
W rite with
Auto Precharge
(B-Bank)
Precharge
( A- B an k )
:Don't Care
*Note : 1. BRSW mode is enabled by setting A9 “High” at MRS (Mode Register Set).
At the BRSW Mode, the burst length at write is fixed to “1” regardless of programed burst length.
2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated.
Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command.
The next cycle is also starts the precharge.
3. WPB function is also possible at BRSW mode.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6
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