M32L1632512A Datasheet, PDF (17/54 Pages) List of Unclassifed Manufacturers – 256K x 32 Bit x 2 Banks Synchronous Graphic RAM

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M32L1632512A
DEVICE OPERATIONS (Continued)
being low matters, all the other inputs including
clock are ignored to remain in the refresh.
The self refresh is exited by restarting the external
clock and then asserting high on CKE. This must be
followed by NOP’s for a minimum time of tRC
before the SGRAM reaches idle state to begin
normal operation. If the system uses burst auto
refresh during normal operation, it is recommended
to use burst 2048 auto refresh cycles immediately
after exiting self refresh.
DEFINE SPECIAL FUNCTION(DSF)
The DSF controls the graphic applications of
SGRAM. If DSF is tied to low, SGRAM functions
as 256K x 32 x 2 Bank SDRAM. SGRAM can be
used as an unified memory by the appropriate DSF
command. All the graphic function mode can be
entered only by setting DSF high when issuing
commands which otherwise would be normal
SDRAM commands.
SDRAM functions such as RAS Active, Write and
WCBR change to SGRAM functions such as RAS
Active with WPB, Block Write and SWCBR
respectively, see the sessions below for the graphic
functions that DSF controls.
SPECIAL MODE REGISTER SET(SMRS)
There are two kinds of special mode registers in
SGRAM. One is color register and the other is
mask register. Those usage will be explained at
“WRITE PER BIT” and “BLOCK WRITE”
session. When A5 and DSF goes high in the same
cycle as CS , RAS , CAS and WE going low,
load color register is filled with color data for
associated DQ’s through the DQ pins. If both A5
and A6 are high at SMRS, data of mask and color
cycle is required to complete the write in the mask
register and the color register at LMR and LCR
respectively. The next color of LMR and LCR, a
new commands can be issued. SMRS, compared
with MRS, can be issued at the active state under
the condition that DQ’s are idle. As in write
operation, SMRS accepts the data needed
through DQ pins. Therefore it should be
attended not to induce bus contention. The more
detailed materials can be obtained by referring
corresponding timing diagram.
WRITE PER BIT
Write per bit(i.e. I/O mask mode) for SGRAM
is a function that selectively masks bits of data
being written to the devices. The mask is stored
in an internal register and applied to each bit of
data written when enable. Bank active command
with DSF=High enable write per bit for the
associated bank. The mask used for write per bit
operations is stored in the mask register
accessed by SWCBR (Special Mode Register
Set Command). When a mask bit=0, the
associated data bit is unaltered when a write
command is executed and the write per bit has
been enable for the bank being written. No
additional timing conditions. Write per bit
writes can be either masking is the same for
write per bit and non-WPB write.
BLOCK WRITE
Block write is a feature allowing the
simultaneous writing of consecutive 8 columns
of data within a RAM device during a single
access cycle. During block write the data to be
written comes from the internal “color” register
and DQ I/O pins are used for independent
column selection. The block of column to be
written is aligned on 8 column boundaries and is
defined by the column address with the 3 LSB’s
ignored. Write command with DSF=1 enable
block write for the associated bank. The block
width is 8 column where column =”n” bits for
by “n” part. The color register is the same width
as the data port of the chip. It is width via a
SWCBR where data present on the DQ pins is
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6
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