M32L1632512A Datasheet, PDF (40/54 Pages) List of Unclassifed Manufacturers – 256K x 32 Bit x 2 Banks Synchronous Graphic RAM

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M32L1632512A
Page Read Cycle at Different Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
CS
*No te1 `
HIGH
RAS
CAS
*N ot e2 `
ADDR
RAa
CAa RBb
CBb
CAc
CBd
CAe
A10
A9
RAa
RBb
WE
DSF
DQM
LOW
DQ CL=2
CL = 3
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1
Row Active
( A- B an k )
Row Active
( B- Ban k )
Read
(A- Bank)
Read
(B- Bank)
Read
(A- Bank)
Read
Read
Pr echar ge
(B-Bank) (A-Bank) ( A-Bank)
:Don't Care
*Note : 1. CS can be don’t care when RAS , CAS and WE are high at the clock high going edge.
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6
40/54