M32L1632512A Datasheet, PDF (51/54 Pages) List of Unclassifed Manufacturers – 256K x 32 Bit x 2 Banks Synchronous Graphic RAM

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M32L1632512A
Self Refresh Entry & Exit Cycle
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CLOCK
CKE
*Note 2
*Note 1
*N ot e 3
*Note 4
tSS
tRCmin
*Note 6
tS S
CS
*Note 5
RAS
*Note 7
CAS
ADDR
*Note 7
A10
A9
WE
DSF
DQM
DQ
Hi-Z
Self Refr esh Entry
Hi-Z
Self R ef resh Exit
Auto Refresh
*Note : TO ENTER SELF REFRESH MODE
1. CS , RAS & CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.
3. The device remains in self refresh mode as long as CKE stays “Low”.
cf.) Once the device enters self refresh mode minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5. CS starts from high.
6. Minimum tRC is required after CKE going high to complete self refresh exit.
7. 2K cycle of burst auto refresh is required before self refresh entry and after self refresh exit
if the system uses burst refresh.
:Don't Care
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6
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