M32L1632512A Datasheet, PDF (21/54 Pages) List of Unclassifed Manufacturers – 256K x 32 Bit x 2 Banks Synchronous Graphic RAM

$%
M32L1632512A
3. CAS Interrupt (I)
*Note1
1)Read interrupted by Read (BL=4)
CLK
CMD
RD RD
ADD
A
B
DQ(CL2)
QA0 QB0 QB1 QB2 QB3
DQ(CL3)
tCC D
*N ot e 2
QA0 QB0 QB1 QB2 QB3
2)Write interrupted by(Block ) Write (BL=2)
CLK
CMD
ADD
DQ
WR WR
tCCD *Note 2
A
B
DA0 DB0 DB1
tCDL
*Note 3
WR BW
tCCD *Note 2
A
B
*N ot e 4
DC0 Pixel
tCDL
*Note 3
4)Block Write to Block Write
CLK
CMD
ADD
DQ
BW NOP BW
Note 7
A
X
B
Pixel
Note 4
Pixel
tBWC
*Note 6
3)Write interrupted by Read (BL=2)
DQ(CL2)
DQ( CL 3)
W R RD
tCCD *Note 2
A
B
DA0
DB0 DB1
DA0
tCDL
*Note 3
DB0 DB1
*Note : 1. By “Interrupt”, It is possible to stop burst read/write by external before the end of burst.
By “ CAS Interrupt”, to stop burst read/write by CAS access ; read, write and block write.
2.tCCD : CAS to CAS delay.(=1CLK)
3.tCDL : Last Data in to new column address delay.(=1CLK)
4.Pixel : Pixel mask.
5.tCC : Clock cycle time.
6.tBWC : Block write minimum cycle time.
7.Other Bank can be active or precharge.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6
21/54