M32L1632512A Datasheet, PDF (37/54 Pages) List of Unclassifed Manufacturers – 256K x 32 Bit x 2 Banks Synchronous Graphic RAM

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M32L1632512A
Page Read & Write Cycle Same Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
HIGH
CS
RAS
tRCD
CAS
AD DR
Ra
Ca0
Cb0
*Note2
Cc0
Cd0
A1 0
A9
Ra
WE
DSF
DQM
*Note2
tCDL
*Note1
tRDL
*Note3
DQ CL=2
Qa0 Qa1 Qb0 Qb1
Dc0 Dc1 Dd0 Dd1
CL = 3
Qa0 Qa1 Qb0
Dc0 Dc1 Dd0 Dd1
Row Active
( A- B an k )
Rea d
Rea d
(A-Bank) (A-Bank)
W rit e
Write
Precharge
(A-Bank) (A- Bank) (A-Bank)
:Don't Care
* Note : 1.To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus
contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
Input data after Row precharge cycle will be masked internally.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6
37/54