AMIS-53050 Datasheet, PDF (97/107 Pages) AMI SEMICONDUCTOR – Frequency Agile Transceiver

AMIS-53050 Frequency Agile Transceiver
Data Sheet
7.2.9.3. Use ID Enabled, CRC Enabled, LOP Enabled
Table 108: Receive
Parameter Action
ID
Data interface immediately ready after ID detected
CRC
As soon as the ID is validated, the CRC starts processing the data
LOP
The LOP is received
The rest of the received data packet is buffered into memory
CRC
invalid
The last byte is the CRC and if invalid, the receiver waits for a command from the external host controller, or if the receiver
came from idle it will return to receive
CRC valid Receiver returns to previous state and an interrupt is issued to the external controller
The data interface is started and the data is sent to the controller, except for the CRC
Table 109: Transmit
Parameter
Buffered transmit
Transmit
ID
CRC
LOP
CRC byte
Action
If buffered transmit is selected, the AMIS-53050 will open the data interface and transfer all TX data into memory with
AMIS-53050 as master or external controller as master
Transmit command (or end of TX data transfer) immediately powers the transmitter on
Transmits preamble (length of preamble as specified)
Transmits the SOF and the ID
The CRC begins processing the data with the ID
Starts data interface and uses a synchronous clock to clock in the TX data (Master only)
or clocks data out of memory (buffered TX)
The first byte is defined to be the LOP of the packet
At the end of the packet, the data stops and the CRC value is sent
After the packet is transmitted, the transmitter waits for a command from the external host controller
Figure 51: Data Interface Protocol (ID, LOP and CRC)
AMI Semiconductor – Jan. 07, M-20639-002
97
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