AMIS-53050 Datasheet, PDF (104/107 Pages) AMI SEMICONDUCTOR – Frequency Agile Transceiver

AMIS-53050 Frequency Agile Transceiver
Data Sheet
10.0 Register Definition
Table 118 contains the addresses for all of the internal registers. Once the EE has been written, the POR states for the registers
become the data last written. Should the CheckSum fail, all registers will return to the POR state shown and an error flag will be written
to a status register.
Table 119: Register List
Address
R/W
Register Name
Hex
Dec
Description
POR State EE Section
R/W 0x00 0
Command
Instruction register
0000_0000
6.2
R/W 0x01 1
Status/Flag1
Part status, flags
0000_0000
6.4.5.1
R/W 0x02 2
Status/Flag2
Part status, flags
0000_0000
6.4.5.2
R/W 0x03 3
Chip address 1
Upper 8 bits of chip address
0000_0000 X
7.1.1
R/W 0x04 4
Chip address 0
Lower 8 bits of chip address
0000_0000 X
7.1.2
R/W 0x05 5
RF divider
Integer portion of RF frequency
0000_0000 X
6.4.1.1
R/W 0x06 6
RF frequency 2
Upper 8 bits of RF fraction
0000_0000 X
6.4.1.2
R/W 0x07 7
RF frequency 1
Center 8 bits of RF fraction
0000_0000 X
6.4.1.3
R/W 0x08 8
RF frequency 0
Lower 8 bits of RF fraction
0000_0000 X
6.4.1.4
R/W 0x09 9
Peak deviation 1
Upper 8 bits of FM deviation
0000_0000 X
6.4.1.5
R/W
0X0A 10 Peak deviation 0
Lower 8 bits of FM deviation
0000_0000 X
6.4.1.6
R/W
0x0B 11 Data rate / format Set discrete data rate and encoding option 0000_0000 X
7.1.3
R/W
0x0C
12
General options A
General options for interface, POR state,
etc.
0000_0000
X
7.1.4
R/W
0x0D
13
General options B
General options for interface, POR state,
etc.
0000_0000
X
7.1.5
R/W 0x0E 14 RX config
Receiver options
0000_0000 X
6.5.1.1
R/W 0x0F 15 TX config
Transmit options
0000_0000 X
6.6.1
R/W 0x10 16 Idle config
Idle mode options
X
6.7.1
R/W 0x11 17 Sniff config
Sniff mode options
1011_0100 X
6.7.2.1
R/W 0x12 18 Sniff interval
Interval between Sniff cycles
0000_1010 X
6.7.2.2
R/W 0x13 19 Energy dwell time Length of time to dwell in sniff mode
0000_0000 X
6.7.2.3
R/W
0x14 20 Code dwell timer
Number of bit times to wait for code
after energy detect
R/W
0x15 21 Energy threshold
Threshold for wake on RSSI, sniff
and CCA
0000_0000 X
0000_0000 X
6.5.1.5
6.5.1.2
R/W 0x16 22 Burst config
Burst transmit options
0000_0000 X
6.7.3
R/W 0x17 23 Burst interval
Interval timer for burst transmit
0001_1000 X
6.7.3.1
R/W 0x18 24 Output power
Output power
0001_0000 X
6.6.2
R/W 0x19 25 Start of frame
Byte used for burst transmit/CDR wake up 0001_0000 X
7.1.6
R/W 0x1A 26 Preamble length
Length of CW, or ‘10’
repeated in Burst/TX (BT’s)
0001_0000 X
6.6.3
R/W 0x1B 27 HK config
Housekeeping options register
X
6.7.4.1
R/W 0x1C 28 HK interval
Interval timer for Housekeeping
X
6.7.4.2
R/W 0x1D 29 Slice threshold
Energy threshold for AM DAC mode
data slice
X
6.5.1.4
R/W 0x1E 30 Filter/slice
AM/RSSI filter setting and AM slice mode
X
6.5.1.4
R/W 0x1F 31 CDR options A
Clock and data recovery options A
X
6.5.1.5
R/W 0x20 32 CDR options B
Clock and data recovery options B
1000_0000 X
6.5.1.5
R/W 0x21 33 Crystal trim
Crystal trim
0000_0000 X
6.10.1.1
R/W 0x22 34 LNA trim
LNA input and output matching trim
0000_0000 X
6.10.1.2
R/W 0x23 35 Quick Start trim
Quick Start oscillator trim
0000_0000 X
6.10.1.3
AMI Semiconductor – Jan. 07, M-20639-002
104
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