AMIS-53050 Datasheet, PDF (47/107 Pages) AMI SEMICONDUCTOR – Frequency Agile Transceiver

AMIS-53050 Frequency Agile Transceiver
Data Sheet
desired frequency connected to the VCO pins. There is internal capacitance, which is part of the capacitance for determining the value
of the inductor. The following equation can be used to determine the approximate value of the LC components. Please note that the
VCO is sensitive to the placement of the LC components. The components should be placed as close to the AMIS-53050 as practically
possible (even short traces add significant parasitics) and the traces to the components should be made symmetrical.
The VCO in the AMIS-53050 is a differential negative resistance oscillator (DNRO), commonly found in the literature. It uses an internal
voltage variable capacitor (varactor) in combination with an external L and C to provide the desired frequency. The output frequency is
estimated by:
Where: Ltot and Ctot are the total inductance and capacitance respectively at the VCO pins. This includes the internal capacitance of
approximately 2pF.
The RF PLL is a 24-bit sigma delta based fractional N synthesizer used to provide the LO signal for receive, and alternately a direct RF
output for transmit.
Register descriptions:
RF Divider- The RF frequency of the receiver must be configured. This is done in two steps; the first and second steps pertain
to setting the RF divider and setting the fractional N word, respectively (AMI Semiconductor has produced a program for
determining the values for these registers, AMIS53KfractionalNCalculator)
RF Frequency- Program the three register fractional N word (AMI Semiconductor has produced a program for determining the
values for these registers, AMIS53KfractionalNCalculator)
Peak Deviation- When the data modulation is to be FSK, the two register peak deviation must also be set. The deviation
should be set to a value between one half and one times the data rate. Maximum deviation is about 200kHz for any data rate.
6.4.1.1. RF Divider
Setting the RF channel frequency is done through the RF divider register, along with the RF frequency 2, 1 and 0 registers. The RF
divider register is used to specify the integer portion of the divide value, and the RF Frequency 2, 1 and 0 registers are used to specify
the fraction. The values are calculated as follows:
Where F_Channel is the desired RF center frequency. The value for the RF divider register is found by,
Where integer is the value used for RF divider. The last step is to calculate the fractional value. This is done as,
AMI Semiconductor – Jan. 07, M-20639-002
47
www.amis.com