AMIS-53050 Datasheet, PDF (84/107 Pages) AMI SEMICONDUCTOR – Frequency Agile Transceiver

AMIS-53050 Frequency Agile Transceiver
Data Sheet
The Manchester option bit configures the AMIS-53050 to transmit and receive in the Manchester encoded format, while the data
interface remains NRZ.
If a data rate other than one of the available discrete rates is desired, the user should set the use custom bit, and then program the
custom data rate register for the desired data rate. When the use custom data rate option is enabled, it is up to the user to set the
correct sample clock frequency in the CDR options B register, set clock recovery loop filter settings, and if using the PLL based FSK
detector, set the PLL detector loop filter.
Note: For data rates that are near one of the pre-defined data rates, a discrete data rate could first be chosen, the ROM2REGS
command given to load all of the settings for the various blocks for that data rate and then the custom data rate option enabled and the
new data rate information entered.
For example, if the desired data rate is 100kbps, set DDRATE to 110 for 96kbps operation. Next, issue the ROM2REGS command in
the command register. All of the proper settings for the clock and data recovery circuit for a 96k data rate will be loaded into the working
registers from ROM (sample clock frequency, clock recovery loop filter settings). Finally, enable the use custom option, and program
data rate 1, and 0 with the value for a 100k data rate.
Custom frequency is set in data rate 1 and data rate 0. If custom is 0, ROM contents for selected discrete data rate are loaded into data
rate 1 and data rate 0.
Table 87: Data Rate/Format - 0X0B [11]
Bit
Name
State Comment
7
NU
6
NU
5
NU
1
Enables user programmable data rate
4
Use custom
0
1
Manchester encoding selected
3
Manchester
0
NRZ encoding selected
000
1.2kbps
001
2.4kbps
010
4.8kbps
2:0
DDRATE [2:0]
011
100
9.6kbps
19.2kbps
101
57.6kbps
110
96kbps
111
128kbps
7.1.4. General Options A
The general options A register contains a number of options that specify the operation of the part in its various modes.
Standby Mode: Determines whether the crystal oscillator is enabled during standby. For applications relying on the
AMIS-53050 to provide and external host controller with a system clock, this bit should be enabled, and is the default state.
POR State: Specifies the power on state of the device. Once this has been stored into EE, the device will power up in the
chosen state after the EE has been shadowed into the working registers.
Pull up Disable: For applications not using an open drain type driver to drive the register interface pins (SDATA, SCLK and
SSN) the pull-ups on these pins can be disabled via this option bit to save power.
Temperature Compensation: When enabled, the ADC output for the temperature sensor is used to compensate the RF
center frequency for crystal frequency error. A new correction factor is calculated each time the ADC performs a new
conversion on the temperature sensor.
CRC Enable: Enables internal CRC checking in RX, and appends a CRC in TX.
AMI Semiconductor – Jan. 07, M-20639-002
84
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