AMIS-53050 Datasheet, PDF (86/107 Pages) AMI SEMICONDUCTOR – Frequency Agile Transceiver

AMIS-53050 Frequency Agile Transceiver
Data Sheet
Table 89: General OptionsB - 0X0D [13]
Bit Name
7
4-Wire data interface
6
Data interface slave master
5,4 _{Data interface clock frequency}
3
Default LOP
2
RXTX sampling edge
1,0 _{System clock output frequency}
State
1
0
1
0
11
10
01
00
1
0
1
0
11
10
01
00
Comment
Enabled
AMIS-53050 is slave
AMIS-53050 is Master, clock speed determined by bits 5, 4
1MHz
500kHz
100kHz
Baud clock
Data packet length is defined by the value of the default LOP
register
LOP must be sent with the data packet
Data bits are sampled on the rising edge of DCLK on the interface
Data bits are sampled on the falling edge of DCLK on the interface
12MHz (24MHz external crystal)
6MHz (24MHz external crystal)
3MHz (24MHz external crystal)
Off
7.1.6. Start of Frame
The start of frame byte is transmitted when this register is non-zero. It’s used as an aid for the receiver clock and data recovery circuit in
modes where the fast phase alignment feature is enabled. The data pattern required is different for different data modulations as
discussed in Table 35.
Table 90: Start of Frame - 0X19 [25]
Bit Name
Comment
7:0 _{SOF [7:0]}
8-bit code sent prior to chip ID in TX and burst
7.1.7. Data Rate 1
The data rate 1 and data rate 0 registers are used to set user defined data rates. These registers are loaded from ROM when a
discrete data rate is selected. The following equation is used to calculate the value for CUST_DR:
where
DataRate is the desired data rate, and F_{sample_clock} is the frequency selected for the sample clock. This register is
loaded with the discrete rate if selected.
Table 91: Data Rate1 - 0X29 [41]
Bit Name
Comment
7:0 _{CUST_DR [15:8]} Upper byte of user defined data rate/discrete data rate
7.1.8. Data Rate 0
Table 92: Data Rate0 - 0X2A [42]
Bit Name
Comment
7:0 _{CUST_DR [7:0]} Lower byte of user defined data rate/discrete data rate
AMI Semiconductor – Jan. 07, M-20639-002
86
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