AMIS-53050 Datasheet, PDF (25/107 Pages) AMI SEMICONDUCTOR – Frequency Agile Transceiver

AMIS-53050 Frequency Agile Transceiver
Data Sheet
5.6 ADC
The ADC is a successive approximation analog to digital converter, using an internal 8-bit DAC as the reference. The ADC data for the
selected input channel(s) will be stored in the associated register, allowing for external access to the conversion data through the serial
interface. Commands in the control register allow for single or continuous operation of the ADC. The ADC results can also be read and
automatically transmitted to another device using the burst transmit mode.
A voltage regulator generates the 2.0V reference for the ADC and DAC based upon an internal bandgap voltage source. The ADC has
six inputs, two of which are available for use in the designer’s application.
5.7 Control Interface Serial Bus
The internal registers of AMIS-53050 can be accessed via a 3-wire (requires the –002 version of the AMIS-53050) or 2-wire I²C
interface, respectively. In this case, the states of the three lines, SDATA, SCLK and SSN, and hence the type of interface are
automatically detected and configured by the transceiver’s control logic. This configuration will be valid as long as power is not removed
or a reset function is not initiated.
I²C: If SSN is high and an I²C start bit is detected, I²C mode is enabled
SPI: If SSN is low, and a negative edge on SCLK detected, SPI mode is enabled
The AMIS-53050 is designed to conform to the Philip Semiconductor I²C standard, with the AMIS-53050 as the slave device.
Figure 13: I²C Serial Bus Connections
AMI Semiconductor – Jan. 07, M-20639-002
25
www.amis.com