AMIS-53050 Datasheet, PDF (94/107 Pages) AMI SEMICONDUCTOR – Frequency Agile Transceiver

AMIS-53050 Frequency Agile Transceiver
Data Sheet
The chip ID is a 16-bit word which can be programmed in registers three and four. In receive mode, when the use ID bit in general
options A is set, the AMIS-53050 will not begin exporting or buffering data until a valid ID matching the value stored in the chip address
registers is received. The ID is used in more advanced modes of operation for byte alignment. In addition to waking on its own unique
ID, the AMIS-53050 will also wake on a pre-defined global chip ID. The default value for the global ID is in the register table. This value
can be overwritten, but is not stored in EE so care must be taken when overwriting the value.
With the use ID bit enabled in transmit mode, the AMIS-53050 will transmit the chip ID prior to enabling the data interface. An additional
option bit in the TX config register allows selection of either the chip ID or global ID value for transmit.
In either transmit or receive, when the use ID bit is enabled without LOP enabled, the AMIS-53050 will not buffer data. Hence when
enabled stand alone, the data interface must be configured with the AMIS-53050 as the master.
7.2.6. Length of Packet Enable
The length of the packet enable (LOP) bit located in general options A, enables the AMIS-53050 to buffer packets. The use ID bit must
be used in conjunction with LOP to allow the receiver to byte align on incoming data.
In receive mode with the LOP enabled, the AMIS-53050 will interpret the first byte following either a valid chip ID, or global ID to be the
length of the incoming packet. This byte specifies the number of bytes following the LOP to be received (non-inclusive of the CRC if
enabled). When enabled, the AMIS-53050 will buffer the incoming packet into internal RAM. Following reception of the last byte of the
packet, an interrupt is issued on the interrupt pin, and depending on the configuration of the data interface, the packet will either be sent
out of the data interface by the AMIS-53050 as master, or it will wait for the external host controller to stream the packet out as the
master.
LOP, in transmit mode, enables the buffering of the TX packet. Once the DSSN is pulled low by the AMIS-53050, the first byte received
into the part is expected to be the LOP byte. Transmission continues until the AMIS-53050 has determined that all bytes have been
received, at which point the data interface is disabled and the AMIS-53050 will return to standby. The actual loading of the data packet
depends on the data interface setup as to whether the AMIS-53050 is master or slave.
7.2.7. CRC Enable
The CRC enable located in general options A is the final tier of intelligence for the AMIS-53050 packet handling capability. In order for
the AMIS-53050 to do CRC checking, this option must be used in conjunction with both use ID and LOP enable. Operation of the
interface for both receive and transmit with the CRC enabled is no different from that explained under the LOP enabled section. With
the CRC enabled, the AMIS-53050 will append the calculated CRC in transmit as the last byte. In receive mode, interrupts to the
external controller will only be issued for packets passing the CRC.
7.2.8. SOF Byte
Table 103: Suggested SOF
Modulation
Detector
AM
RSSI
FM (<20kbps) PLL
FM (>20kbps) FFT
Coding
NRZ
Manchester
1 0 pattern
NRZ
Manchester
Preamble
CW
CW
1 0 pattern
Repeating 1/0
All 1’s or 0’s
SOF
55 (HEX)
0A (HEX)
Not required
Not required
55 (HEX) or AA (HEX)
Depending on whether the mode of operation is AM or FM, NRZ or Manchester, it may be necessary for a SOF byte to precede the
chip ID. This byte is user programmable, and is used to ensure proper CDR operation and bit alignment prior to reception of the chip
ID. When the contents of the SOF byte register are loaded to any non-zero value, this byte will be transmitted prior to the chip ID. For
modes not requiring the SOF byte, setting this register to 00h will prohibit transmission of this byte. More information on when the SOF
byte is required is in the clock and data recovery section.
AMI Semiconductor – Jan. 07, M-20639-002
94
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