AMIS-53050 Datasheet, PDF (13/107 Pages) AMI SEMICONDUCTOR – Frequency Agile Transceiver

AMIS-53050 Frequency Agile Transceiver
Data Sheet
Table 7: Pin Definitions (Continued)
Pin#
-001
-002
17
Drxtx
Drxtx
18
Dclk
Dclk
19
SYSclk
SYSclk
20
Dvss
Dvss
21
Dvdd
Dvdd
22
CoreReg
SSN
23
SCLK
SCLK
24
SDATA
SDATA
25
xBURST xBURST
26
LOOPout LOOPout
27
LOOPin
LOOPin
28
LOvss
LOvss
29
LOn
LOn
30
LOp
LOp
31
LOvdd
LOvdd
32
RFvdd
RFvdd
Pin Type
Digital IO
Digital IO
Digital output
Ground
Power
Digital
Digital
Digital
Digital input
Analog
Analog
Ground
Analog
Analog
Power
Power
Description
Serial data input (Transmit) or output (Receive)
Recovered clock output (Data interface clock)
System clock output
Ground for the digital circuits
Vdd supply for the digital circuits
-001 (pin bonded for a decoupling capacitor for the internal regulator)
-002 (pin is bonded to bring out the SSN bus enable for the control bus)
Bi-directional clock for the 2-wire serial interface
Bi-directional data for the 2-wire serial interface
Active low input interrupt that will immediately cause a Burst transmission
Output to the optional external loop filter
Input from the optional external loop filter
Ground for the local oscillator circuits
Negative side of the VCO tank
Positive side of the VCO tank
Vdd supply for the local oscillator circuits
Vdd supply for the RF circuits
3.2.2. Block Diagram/Pin Definition
Figure 2: Block Diagram/Pin Definition *
* Not actual package markings. Please see marking format in 3.2.3.3.
AMI Semiconductor – Jan. 07, M-20639-002
13
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