AMIS-53050 Datasheet, PDF (89/107 Pages) AMI SEMICONDUCTOR – Frequency Agile Transceiver

AMIS-53050 Frequency Agile Transceiver
Data Sheet
Figure 45: Data Protocol Timing (AMIS-53050 as Master)
Table 97: Serial Data Timing
Symbols
TINT
Tdssn
TCLK
TData
TCend
TDend
Data Bit
Description
Interrupt to the external host controller to indicate data packet received
Delay time from the interrupt to the time that DSSN is active low
Time from DSSN going active and the start of the data clock
Time from DSSN going active and the first bit of the data appears
Time from the last clock pulse and DSSN goes inactive
Time from the last data bit ends and the DSSN signal goes inactive
Data bit period
Typical
5
Register (Idle Config)
Immediate
Immediate
Immediate
Immediate
Register (gen opts B)
Units
uS
Bit times
Clock period
Note: These times are when the AMIS-53050 controls the timing as the master. When the external Host controller is configured as the
master, these times will change.
AMI Semiconductor – Jan. 07, M-20639-002
89
www.amis.com