AMIS-53050 Datasheet, PDF (96/107 Pages) AMI SEMICONDUCTOR – Frequency Agile Transceiver

AMIS-53050 Frequency Agile Transceiver
7.2.9.2. Use ID Enabled, No CRC, LOP Enabled
Table 106: Receive
Parameter
Action
ID
Data interface immediately ready after ID detected
LOP
Receiver loads rest of packet into buffer memory
After last data byte is received, radio returns to the previous state
An interrupt is issued to the external controller/microprocessor
Data is transferred out the port with the AMIS-53050 as Master or the external controller as Master
No CRC
Error checking is not performed and CRC is not attached to packet
Table 107: Transmit
Parameter
Action
Buffered
Transmit
If buffered transmit is selected, the AMIS-53050 will open the data interface and transfer all TX data
into memory with AMIS-53050 as Master or external controller as master
Transmit
Transmit command (or end of TX data transfer) immediately powers the transmitter on
Transmits preamble (length of preamble as specified)
ID
Transmits the SOF and the ID
Starts data interface and uses a synchronous clock to clock in the TX data (master only)
or clocks data out of memory (buffered TX)
After the packet is transmitted, the transmitter returns to standby state
Data Sheet
Figure 50: Data Interface Protocol (ID and LOP)
AMI Semiconductor – Jan. 07, M-20639-002
96
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