AMIS-53050 Datasheet, PDF (38/107 Pages) AMI SEMICONDUCTOR – Frequency Agile Transceiver

AMIS-53050 Frequency Agile Transceiver
6.1.4.2. Single Register Write
Data Sheet
Figure 27: Single Control Data Read/Write with the I²C Interface
The master device issues the start condition, then issues the device address, and then issues the single R/W bit, a logic low state. This
indicates to the addressed slave receiver that a byte with a register address will follow after the slave has generated an acknowledge bit
during the ninth clock cycle. Therefore, the next byte transmitted by the master is the register address to be written with data. After
receiving another acknowledge signal from the AMIS-53050, the master device will transmit the data word to be written, and the
AMIS-53050 will acknowledge again. The write cycle ends with the master generating a stop condition.
A similar approach is used to read a register value. The Master device issues the start condition, then issues the device address and
then issues the single R/W bit, a logic low state. This indicates to the addressed slave receiver that a byte with a register address will
follow after the slave has generated an acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master
is the register address to be read. After receiving another acknowledge signal from the AMIS-53050, the master device will immediately
follow with another start sequence, however, the R/W bit is now set high, telling the slave device that the master wants the contents of
the register (addressed with the write command) to be placed on the SDA bus line. After the Master reads the eight bits of data, the
master does not acknowledge but sends the stop sequence.
AMI Semiconductor – Jan. 07, M-20639-002
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