AMIS-53050 Datasheet, PDF (36/107 Pages) AMI SEMICONDUCTOR – Frequency Agile Transceiver

AMIS-53050 Frequency Agile Transceiver
Data Sheet
Figure 25: Single Control Register Read/Write Using the 3-Wire Interface
Figure 25 shows a single read or single write control data transfer. The operation starts with SSN transitioning low to indicate a start of
transfer. The first two bits transferred are the instruction for the slave interface of the AMIS-53050, namely IN1 and IN0, respectively.
Following the instruction are the six address bits to specify which address to read or write. If the instruction is to write to a register, the
register location is A<5:0> and the data is specified with the next eight bits, D<7:0>. If the operation is a read function, the slave output
buffer is enabled at the end of the address bits, and the data bits D<7:0> are buffered out of the part MSB first.
For single read/write, the SSN line can remain active between successive read and write operations.
AMI Semiconductor – Jan. 07, M-20639-002
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