AMIS-53050 Datasheet, PDF (34/107 Pages) AMI SEMICONDUCTOR – Frequency Agile Transceiver

AMIS-53050 Frequency Agile Transceiver
Data Sheet
6.1.2. Serial Control Interface: Configuration
The AMIS-53050’s control logic can automatically detect the type of interface used for the serial control bus. The interface pins are
then given the definitions as shown in Table 14. The detection scheme is based on the status of the device pins, as shown in Figure
23.
Table 14: Control Port Pin Definitions
Pin Name
I2C Mode
SCLK
SCL
SDATA
SDA
SSN
Internal pull up
3-Wire Mode
SCLK
R/W controlled
SSN
Figure 23: Control Interface Selection
Addressing the part with the desired protocol will result in the configuration of the interface settings. After the first communication with
the device, the selection is locked until power is removed. The internal logic for determining which protocol to use on initial power-up is
as follows:
I²C: If SSN is high and an I²C start bit is detected, I²C mode is enabled.
3-wire: If SSN is low, and a negative edge on SCLK detected, 3-wire mode is enabled.
The internal pull-ups on SCLK and SDATA can also be disabled for I²C applications using external pull-ups.
Table 15: Control Interface Pull Up Control
Mode
SCLK, SDATA Pull Ups
I²C
Controlled by bit 3 of the general
options A register
3-wire
Controlled by bit 3 of the general
options A register
SSN Pin Configuration
Not used (internal pull up)
SSN: normal mode
AMI Semiconductor – Jan. 07, M-20639-002
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