AMIS-53050 Datasheet, PDF (83/107 Pages) AMI SEMICONDUCTOR – Frequency Agile Transceiver

AMIS-53050 Frequency Agile Transceiver
Data Sheet
The AMIS-53050 employs two different data interfaces. Transmit and receive data is exchanged with an external controller through
either a 3-wire or a 4-wire SPI like interface. Selecting the interface, 3-wire or 4-wire is done by writing to Bit 7 of the general options B
register.
SPI serial data interface
3-wire serial data interface
AMIS-53050 can be the slave or master
Register descriptions:
Chip Address- Allows a unique value to be transmitted and received with the data packet to identify a unique radio.
Fixed Data Rates- Select the options for one of several fixed data rates.
General Options A- Configure the interface options.
General Options B- Configure the interface options.
Idle Config- Sets a wait time between:
1. The INT signals a data transfer is ready and the DSSN line starts that transfer.
2. The Idle command and the SYSclk clock stops (allows for the external HOST controller to finish tasks).
Start of Frame- Set a code value that indicates the start of a data packet.
Preamble Length- Select a type of preamble and set the length in bits. (see Section 6.6.3)
Custom Data Rates- Configures parameters for data rates that are not one of the fixed data rates.
CRC Polynomial- Value of the CRC polynomial.
Default Length of Packet- Set a default length for packets. Note: when the LOP or the default LOP (and the default LOP is
enabled, bit 3 of the general optionsB register) is anything other than zero, the AMIS-53050 is in packet mode.
Broad Cast ID- A general chip ID allowing for transmissions to be received by all radios.
7.1.1. Chip Address MSB1
The 16 bit ID that can be used for several purposes in the AMIS-53050 .
Table 85: Chip Address1 - 0X03 [3]
Bit Name
Comment
7:0 _{Chip_Add [15:8]}
Upper byte of chip address
7.1.2. Chip Address LSB
Table 86: Chip Address0 - 0X04 [4]
Bit Name
Comment
7:0 _{Chip_Add [7:0]}
Lower byte of chip address
7.1.3. Data Rate/Format
The data rate/format register is used to select the data rate and format for both receive and transmit. The DDRATE[2:0} option bits
allow selection of one of eight pre-programmed data rates. When one of the discrete data rates is selected, the ROM2REGS command
is used to load clock and data recovery settings for the desired data rate into their associated registers.
AMI Semiconductor – Jan. 07, M-20639-002
83
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