AMIS-53050 Datasheet, PDF (61/107 Pages) AMI SEMICONDUCTOR – Frequency Agile Transceiver

AMIS-53050 Frequency Agile Transceiver
Data Sheet
Register descriptions:
Data Rate- Can be specified in the discrete data rate register, or specified as a 16-bit word for a user defined data rate (see
Section 7.1.3).
Peak Deviation- The peak deviation register stores the value to be used for both transmit and receive. In the FFT FM receive
mode, this value is used to set-up the FFT bins (see Sections 6.4.1.5 and 6.4.1.6).
PLL Detector Loop Filter- For the discrete data rates, the values for the loop filter coefficients are pre-programmed (issue the
command ROM2REGs to have the AMIS-53050 determine these values). For user defined data rates, this value needs to be
calculated. (AMI Semiconductor provides a program, helper.exe, which can help in determining the values for this register.)
CDR Loop Filter- For the discrete data rates, the values for the loop filter coefficients are pre-programmed (issue the
command ROM2REGs to have the AMIS-53050 determine these values). For user defined data rates, this value needs to be
calculated. (AMI Semiconductor provides a program, helper.exe, which can help in determining the values for this register.)
PLL Detector Loop Filter Setting
A program (helper.exe available from AMIS) has been created to aid in the design of loop filter settings.
Table 38: PLL Detector Loop Filter Setting - 0X2B [43]
Bit Name
Comment
7:0 _{PLL_CO [7:0]}
PLL loop filter setting
Table 39: Clock Recovery Loop Filter Setting - 0X2C [44]
Bit Name
Comment
7:0 _{CDR_CO [7:0]}
Clock recovery filter setting
6.5.1.5. Clock and Data Recovery
The AMIS-53050 device performs clock and data recovery for both AM/OOK/ASK and FM/FSK signals. An internal clock in the
AMIS-53050 is programmed to be nearly the same rate as the expected data rate in the incoming signal. This clock is then
synchronized to the incoming data rate by extracting a clock from the data. This loop recovery method recovers data without much of
the jitter and noise associated with wireless communication links.
Before launching headlong into the operation of the detectors, and how to set them up, it is instructive to review the following related
registers, set-up options and their functions.
Register descriptions:
Fast Phase Alignment: In both the AM and PLL based FM modes (lower data rate), the AMIS-53050 can be configured to
quickly acquire phase lock on incoming data. The pattern necessary for the fast phase alignment is simply ‘1010’. This function
can be enabled in the CDR options A register. With this function enabled, the CDR circuit will operate with minimum power
consumption until the ‘1010’ sequence is received. A 32-bit correlation is used to not only recognize the 1010 pattern, but also
to instantaneously provide a phase correction to the clock recovery circuit allowing very fast (less than 4 bit) lock times locking
the incoming data.
Activity Check: This function can be used in conjunction with the fast phase alignment to reset the clock and data recovery
block back into its minimal power consumption mode when no transitions are detected on the data line for a specified period.
The check can be configured for 4, 8 or 16 bit times.
Over-Sampling Clock (Ts Clock): All three detectors use the Ts clock as the sampling clock for the transition from analog to
digital. This clock should be set to the highest rate possible, but not greater than 400x the data rate, to ensure adequate phase
information. For the discrete data rates, this value is pre-programmed for those rates when the ROM2REGS command is
issued.
Data Rate Clamp: The data rate clamp restricts the clock recovery circuit from wandering when an actual signal is not
present, and the phase error signals being generated come only from noise. Small fractional values for the clamp can lead to
longer lock times since the clock recovery PLL may not be able to make as large of a correction as is necessary all at once.
AMI Semiconductor – Jan. 07, M-20639-002
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